1. Technical Field
The present disclosure relates generally to semiconductor devices and their fabrication. In particular, the present disclosure relates to a transistor having asymmetric channel and source/drain regions, where the source and the drain of the transistor comprise different semiconductor materials.
2. Description of Related Art
The need to remain cost and performance competitive in the production of semiconductor devices has resulted in continuous decrease in device scale in integrated circuits. As CMOS devices scale, device to device variation increases dramatically due to, inter alia, dopant fluctuation and process variations. In particular, a major challenge is the improvement of the drive current without, for example, degrading the short channel performance. While strained Si1-xGex leading to current improvements has been described in the prior art, key challenges persist. For example, the short channel effects and off state leakage current are degraded due to the smaller band gap in the Si1-xGex layer.
Thus, the increased device mismatch significantly impacts SRAM stability. In light of the aforementioned difficulties of maintaining SRAM stability, it would be desirable to provide a novel structure and methods of improve SRAM stability and minimum operating voltage (Vmin) of SRAM. Accordingly, the present disclosure is directed to providing an improved transistor having asymmetric channel as well as source/drain regions.